Sr Design Verification Engineer / Verification Lead
Job Description
- The candidates should be having 8 + Years of VLSI Industry experience in the Front end Verification using SV-UVM/OVM Methodology
- The role requires the following attributes in the candidate: Hands-on verification experience and proficiency using System Verilog and OVM/UVM2
- Interact closely with the architecture and design teams, influencing product definition, implementation and validation. Create, define and develop system validation environment and test suites.- Responsible for the development of methodologies, execution of validation test plans, test sequences and directed tests.
- Proven track record in ASIC verification from environment development to tests development
- Experience in development and deployment of verification strategies and methodologies across teams and organizations
- Experience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage.
- Experience with SRAM,DRAMs, Clk-power architectures, AON, Multi clock domains ets is a Plus.
- He should be able to Manage and Co-ordinate with the Off-shore team members.
Date Posted
08/12/2022
Views
4
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