Sr. Staff Engineer - Timing Methodology

Ambiq

Sr. Staff Engineer - Timing Methodology

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Austin TX USA

In-Office

Senior level

Hardware • Internet of Things • Software • Wearables • Semiconductor

Join the Team Powering the Future of Edge AI

The Role

Lead timing methodology and closure for block and SoC levels in modern FinFET/multi-patterning processes. Define flows constraints signoff correlation timing margining glitch noise analysis and collaborate with RTL PnR DFT and post-silicon teams to achieve timing convergence and best-in-class PPA.

Summary Generated by Built In

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010 we've shipped over 300 million units to customers building smarter wearables medical devices IoT products and AI-powered edge applications.

Our cross-functional teams span design research development production marketing sales and operations across Austin Hsinchu Shanghai Shenzhen and Singapore. We move fast tackle hard problems and create space for people to grow through complex meaningful work that shapes the future of technology.

We're looking for self-motivated creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you join us — the intelligence everywhere revolution starts here.

Scope 

As a Sr. Staff Engineer - Timing Methodology you will play a critical role in transforming our cutting-edge designs into silicon reality. You will be responsible for all aspects of timing closure from defining methodology developing flows closing timing at the block level and timing convergence at SOC level as well.

Responsibilities:

In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime.
Own all aspects of timing convergence including Signoff to build timing correlation PVTRc corner definition timing margining extraction signoff timing analysis glitch noise analysis timing ECOs and interplay and tradeoff with power.
Own define and drive constraints in collaboration with RTL and IP Vendors.Have in-depth understanding of all timing collaterals for different type of Ips namely hard IP Stdcell and Memory etc.
Partner with post-si bringup and testing to ensure pre-si timing correlates well to post-si.
Collaborate closely with RTL designers DFT and other stakeholders to achieve best in class PPA.
Continuously improve timing analysis methodologies and scripts to enhance efficiency and flow consistency. Stay at the forefront of advancements in STA and new process nodes

Requirements

Master's degree in Electrical Engineering or Computer Engineering (or a related field)
Minimum of 8 years of experience in Timing Analysis and convergence.
Proven expertise in static timing analysis using industry-standard timing tools like Primetime (Synopsys) or Tempus (Cadence).
In-depth understanding of digital circuit design principles and concepts
Strong proficiency with industry-standard EDA tools (e.g. Synopsys Cadence)
Excellent analytical and problem-solving skills
Ability to work effectively in a team environment and communicate complex technical concepts clearly
Experience with scripting languages (e.g. TCL Python)
Experience with PnR tools like Fusion Compiler (Synopsys) and Innovus (Cadence) is a plus.

Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.

Skills Required

Master's degree in Electrical Engineering Computer Engineering or related field
Minimum of 8 years of experience in Timing Analysis and convergence
In-depth expertise in Timing Methodology and timing closure for FinFET and multi-patterning process technologies
Proven expertise in static timing analysis using Synopsys PrimeTime or Cadence Tempus
Strong proficiency with industry-standard EDA tools (Synopsys Cadence)
Experience with scripting languages such as TCL and Python
In-depth understanding of digital circuit design principles
Excellent analytical and problem-solving skills and effective team communication
Experience with PnR tools like Fusion Compiler (Synopsys) and Innovus (Cadence)
Must be currently authorized to work in the United States without sponsorship

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The Company

HQ: Austin Texas

220 Employees

Year Founded: 2010

What We Do

Ambiq® enables intelligence (AI and beyond) everywhere by delivering the lowest-power semiconductor solutions for battery-powered edge devices. As a pioneer in ultra-low power SoCs Ambiq empowers wearables IoT smart home healthcare and industrial products with always-on energy-efficient intelligence. Backed by our SPOT® technology and global innovation leadership Ambiq is shaping the future of edge AI.

Why Work With Us

Direct influence on silicon architectureSmaller high-impact teamsHardware/software co-design in real timeFaster technical decision cyclesVisible ownership at Staff & Director levelAustin-based collaboration culture

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OnSite Workspace

Building silicon and embedded AI systems requires tight collaboration across firmware hardware validation and architecture teams.We believe the hardest engineering problems are solved through direct daily collaboration.

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