Job Description
Company Overview
Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.
Built on our proprietary sub- and near-threshold technology our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010 we've shipped over 300 million units to customers building smarter wearables medical devices IoT products and AI-powered edge applications.
Our cross-functional teams span design research development production marketing sales and operations across Austin Hsinchu Shanghai Shenzhen and Singapore. We move fast tackle hard problems and create space for people to grow through complex meaningful work that shapes the future of technology.
We're looking for self-motivated creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.
At Ambiq we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.
If that's you join us — the intelligence everywhere revolution starts here.
This role will be on-site 5 days a week in NW Austin.
ScopeWe are seeking an experienced DFT (Design for Testability) Engineer to design implement and optimize test architectures for semiconductor products. This role involves collaborating with design verification and manufacturing teams to ensure products meet testability yield and quality objectives. The successful candidate will own the DFT strategy develop test methodologies and drive continuous improvement in test coverage and manufacturing efficiency.
Responsibilities
- Responsible for scan insertion boundary scan MBIST and ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.
- Develop and implement low-power DFT architecture and infrastructure.
- Generate structural test vectors analyze and improve coverage test time and test cost.
- Perform pre/post-layout scan and MBIST simulations.
- Work with designers on STA physical power and logical issues related to DFT.
- Work with test engineers to bring up test vectors on silicon.
Qualifications
- BS/MS in ECE/EE and at least 10 years of experience in DFT implementation.
- Skilled in different types of DFT structures including scan (Stuck-At At-Speed Path-Delay) scan compression boundary scan and MBIST.
- Experience in creating and implementing hierarchical DFT architecture in complex SoC.
- Experience in Low-Power DFT and MBIST.
- Plan generate and verify Memory Repair Patterns using Tessent MBIST flow.
- Experience in test time and test coverage analysis for scan and MBIST patterns.
- Experience in working with test engineering team to bring up production test program.
- Extensive knowledge of timing concepts and constraint development.
- Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.
- Experience in processing failure files from ATE and perform diagnosis in ATPG tool.
- Experience with using Cadence Genus and Modus compression to generate low-power SCAN and ATPG patterns.
- Experience in RTL is required.
- Experience in scripting like Tcl and Perl/Python is preferred.
- Experience with GLS (gate level simulation) is preferred.
- Motivated self-driven engineer with attention to detail.
- Strong verbal and written English communication skills.
Must be currently authorized to work in the United States for any employer. We do not sponsor or take over sponsorship of employment visas (now or in the future) for this role.
Skills Required
- BS/MS in ECE/EE with at least 10 years of DFT implementation experience
- Skilled in DFT structures including scan (Stuck-At At-Speed Path-Delay) scan compression boundary scan and MBIST
- Experience creating and implementing hierarchical DFT architecture in complex SoC
- Experience in Low-Power DFT and MBIST
- Plan generate and verify Memory Repair Patterns using Tessent MBIST flow
- Experience in test time and test coverage analysis for scan and MBIST patterns
- Experience working with test engineering team to bring up production test program
- Extensive knowledge of timing concepts and constraint development (STA)
- Experience developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments
- Experience processing failure files from ATE and performing diagnosis in ATPG tools
- Experience using Cadence Genus and Modus compression to generate low-power SCAN and ATPG patterns
- Experience in RTL
- Experience in scripting (Tcl and Perl/Python)
- Experience with GLS (gate level simulation)
- Motivated self-driven engineer with attention to detail
- Strong verbal and written English communication skills
- Must be currently authorized to work in the United States for any employer (no visa sponsorship)
Ambiq Compensation & Benefits Highlights
- Healthcare Strength—Medical dental and vision coverage are part of the core package and the health insurance is portrayed positively across the provided information. This indicates dependable core healthcare support.
- Leave & Time Off Breadth—Paid time off and an expanded holiday schedule including a year‑end closure are highlighted. References to PTO accrual and carryover reinforce strong time‑off design.
- Parental & Family Support—Parental leave and family medical leave are explicitly included. This signals structured support for caregiving needs.
Ambiq Insights
What We Do
Ambiq® enables intelligence (AI and beyond) everywhere by delivering the lowest-power semiconductor solutions for battery-powered edge devices. As a pioneer in ultra-low power SoCs Ambiq empowers wearables IoT smart home healthcare and industrial products with always-on energy-efficient intelligence. Backed by our SPOT® technology and global innovation leadership Ambiq is shaping the future of edge AI.
Why Work With Us
Direct influence on silicon architectureSmaller high-impact teamsHardware/software co-design in real timeFaster technical decision cyclesVisible ownership at Staff & Director levelAustin-based collaboration culture
Ambiq Offices
OnSite Workspace
Building silicon and embedded AI systems requires tight collaboration across firmware hardware validation and architecture teams.We believe the hardest engineering problems are solved through direct daily collaboration.
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Date Posted
07/02/2026
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