Sr. IP Design Engineer

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Senior IP Design Engineer

Applicant will have Test, Design and Verification responsibilities for Allegro's internally developed custom memories including: SRAM, ROM, One-Time-Programmable, EEPROM and Flash.

Responsibilities

- Transistor-level circuit design, simulation and testing.

- Create test/validation plan for different sizes of memories.

- Documentation/application note development and customer support.

- Liberty characterization of memory IPs

- Liberty characterization of standard cells

Requirements

• BSEE or MSEE with 5+ years' experience with memory design, circuit simulation and testing; knowledge of transistor level circuit design and layout;
• Knowledge of CMOS fabrication methods and digital circuits;
• Experience with layout parasitic extraction and simulation tools;
• Strong written and verbal communication skills;
• Experience with Unix shell languages; understanding of issues and modeling of variation in deep sub-micron technologies;
• Knowledge of Verilog modeling; familiarity with layout verification tools, design rules, and rule decks.

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At Allegro, we are committed to providing a harassment-free environment of mutual respect to fuel innovation through inclusive thought collaboration. Allegro is an Equal Opportunity Employer and does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, national origin, veteran status, parental status, or any other basis covered by appropriate law. Allegro makes hiring decisions based solely on qualifications, merit, and business needs at the time.