Sr. Manager, Device Engineering

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Job Description

You will be part of Allegro Technology Development department and will lead international team of experienced semiconductor device and process development engineers.

Your responsibilities will include:

• Provide leadership, mentoring, motivation and day-to-day operational management of the device and process development team.
• Work with Senior Management to define and implement wafer technology roadmap for Allegro Business Units.
• Plan and execute new technology development projects with foundries and internal teams.
• Lead the development of Allegro PDK devices and components: HV and Power LDMOS, BJT, CMOS, ESD, memory cells, passives, sensor elements: Hall-effect, GMR, TMR.
• Evaluate foundry PDKs. Define technology design rules.
• Create strategies for process development test vehicles to evaluate devices, process margins, models and reliability.
• Support resolution of customer, yield and reliability issues.
• Participate in product design reviews with design engineers. Perform DRC reviews, formulate layout guidelines.
• Coordinate and deliver technical support to design, product and layout engineers to ensure successful and reliable manufacturing of Allegro products.
• Provide leadership to enhance Allegro process technology and device IP.

Desired skills and experience

• Extensive experience in Semiconductor industry as a process/device engineer, coupled with experience as functional manager of an engineering team.
• A minimum of MS in EE, Device Physics with Ph.D. strongly preferred. A minimum of 5 years in similar role plus a 10+ years of device engineering / process integration experience. Strong background in materials science is a plus.
• Demonstrated experience in leading, motivating and managing small to medium teams of highly skilled engineers in process technology.
• In-depth knowledge and practical understanding of semiconductor process technologies specific to Analog and Mixed-Signal design and products, especially BCD and HV processes. Experience with compound semiconductor technology and devices is a plus.
• Expertise in semiconductor devices including process development, device characterization, reliability, yield enhancement, parametric tuning.
• Deep technical understanding of power devices, LDMOS, BJT's, ESD, standard CMOS. Knowledge of magnetic sensors and technology for Hall-effect, GMR and TMR is preferred.
• Experience in TCAD device and process simulation, familiarity with Cadence EDA tools.
• Good understanding of analog circuits; circuit design experience is a plus.
• Ability to drive third-party technology partners to deliver processes optimized for Allegro's product requirements.
• Ability to define and prioritize work, set goals and meet deadlines for self and others.
• Excellent communication and interpersonal skills with the ability to operate across global time zones and cultures.
• Ability to travel 10-15% of time.

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At Allegro, we are committed to providing a harassment-free environment of mutual respect to fuel innovation through inclusive thought collaboration. Allegro is an Equal Opportunity Employer and does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, national origin, veteran status, parental status, or any other basis covered by appropriate law. Allegro makes hiring decisions based solely on qualifications, merit, and business needs at the time.