Staff Engineer DV

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

Responsibilities:

• Architecting test methodologies applicable to a wide range of CPU designs for CPU memory sub-systems including memory virtualization (Paging and Hypervisors), LoadStore unit, various levels of caches and industry standard bus protocols (e.g., AMBA and Tilelink).
• Creating effective verification strategies for CPU memory system caches.
• Building test plans to implement these strategies, considering issues such as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.
• Developing tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.
• Developing and using unit level test benches that use constrained random stimulus.
• Using assembly code Random test generators to meet verification objectives in single and multi-core CPU environments.
• Writing directed assembly tests as appropriate to test CPU functions.
• Providing technical leadership to verification engineers and coordinating technical teams to execute our verification strategies to meet program goals.
• Collaborating closely with the design team on feature specifications, test plans and failure analysis.

Requirements:

• 10+ years of recent experience with standard verification tools and methodologies (C,UVM, Verdi/DVE, System Verilog, Verilog, Make files, scripting languages, etc.), especially in hands-on testbench development and test suite generation.
• Solid understanding of CPU and SoC memory architecture including memory virtualization (hypervisor, paging), Load-Store unit, various levels of caches, cache coherence protocols, bus interface units, and memory controllers.
• Experience with industry standard system bus protocols (e.g., CHI, ACE, AMBA AXI, AHB, APB) is preferred. Knowledge of Tilelink is a plus.
• A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).
• Ability to effectively assess the design verification metrics, remaining state space to be covered, and efficient methods to achieve verification closure.
• Verification experience in test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
• Ability to learn languages and methodologies that are not part of the industry standard to verification (Scala, Chisel, etc.)
• Understanding of CPU memory systems caches from an architectural level

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.