Staff Mixed Signal Design Engineer HBM

• Define and own micro-architecture for base-die digital subsystems including high-bandwidth memory (HBM) channel support logic boot and initialization sequencing training orchestration configuration and status registers (CSR) telemetry performance counters and reliability features.
• Translate system requirements into timing power and area budgets by partnering with physical layer (PHY) and system architects and maintain clear interface specifications for bus protocols clock-domain crossing (CDC) and reset strategy.
• Implement and integrate synthesizable register-transfer level (RTL) designs in SystemVerilog including multi-channel logic interrupts events register maps scan hooks and design-for-test (DFT) interfaces.
• Ensure robust reset and power-up behavior handle corner cases and maintain clear engineering change order (ECO) pathways.
• Collaborate with design verification (DV) teams to build verification plans achieve coverage goals complete CDC and reset-domain crossing (RDC) checks and debug RTL testbench and gate-level issues.
• Provide guidance on timing constraints exceptions and path intent and refine micro-architecture to resolve timing-critical paths.
• Partner with DFT and test teams to integrate scan memory built-in self-test (MBIST) logic built-in self-test (LBIST) boundary access and debug instrumentation.
• Support post-silicon validation by enabling debug hooks correlating issues to RTL or architecture and driving efficient issue resolution.

• Bachelor's degree in Electrical Engineering or Computer Engineering or equivalent practical experience.
• Typically 10+ years of experience in digital design or system-on-chip (SoC) integration with ownership of complex logic through tape-out.
• Expertise in SystemVerilog RTL design clock and reset architecture clock-domain crossing (CDC) and reset-domain crossing (RDC) methodologies and low-power design concepts.
• Working knowledge of design-for-debug and design-for-test fundamentals and experience coordinating multi-functional technical efforts.

• Experience supporting post-silicon validation through structured debug correlation and issue resolution.
• Experience integrating scan memory built-in self-test (MBIST) logic built-in self-test (LBIST) or related test and debug features.
• Experience developing verification plans and partnering with design verification teams to achieve coverage goals.
• Ability to refine micro-architecture to improve timing and mentor others on constraints and design tradeoffs.

What We Do

We are a world leader in innovative memory solutions that transform how the world uses information to enrich life for all. For over 45 years our company has been instrumental to the world’s most significant technology advancements delivering optimal memory and storage systems for a broad range of applications.

Why Work With Us

Global opportunities team member development and career advancement—Micron invests in you and celebrates your skills a growth mindset and the tenacity to strive. At Micron everyone innovates.