Technical Lead - Product Engineering - HPP

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Technical Lead - Product Engineering - HPP

Join a growing and dynamic IP team and help lead the development of best in class digital and mixed signal IP products. This is a tremendous opportunity to work with an experienced team focusing on development of high-performance IP related to protocols such as PCIe, USB, DPHY and Ethernet PHYs.

The role will be a key leader in organization responsible for IP activities including but not limited to Pre-sales engagement with potential customers, Pre-Silicon integration and Post silicon bring-up and test support for the customers.

This candidate will also be responsible for hiring and growing a team that is the primary interface between customer and CDNS R&D team. Candidate should possess strong leadership skills with ability to manage multiple priorities and guide engineers on day-to-day activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication of status, are must have attributes in this role.

• Primary Responsibilities:
  • Lead and build a team that is primary interface between CDNS IP R&D customer engineering teams.
  • Responsible for supporting integration / customization / post silicon deployment of CDNS SERDES IP subsystems.
  • Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
  • Support PHY and controller SOC integration reviews, and integration questions.
  • Perform RTL and gate level simulations to verify functionality.
  • Assist customers with gate level simulations and timing closure.
  • Develop and optimize comprehensive test automation
  • Participate and run reviews for CDNS documentations and checklists for customers.
  • Update R&D team with the latest customer feedback and competitive analysis.
  • Willing to travel to customer sites worldwide including overseas Travel
  • Working with global (US, west coast and east coast) teams, which work in different time-zones
• Position Requirements:
  • M.S. Electrical/Computer Engineering (or similar degree)
  • 10+ years of overall experience
  • 3+ years technical management experience
  • Experience working with PCIE, Ethernet, 112G or similar interface IP.
  • Verilog RTL design and gate level verification experience.
  • Full understanding of SOC digital design methodology and tools.
  • Synthesis and STA experience, back-end experience is a plus
  • Familiarity with industry standard DFT flows and test methodologies.
  • Familiarity with package and board design. Ability to read schematics and conduct SI/PI reviews for customer board implementation
  • Knowledge of circuits such as Phase Locked Loops, Tx and Rx Equalizers, ADC's etc.
  • Familiar with concepts of Jitter, Noise, and other non-idealities in circuits
• Preferred Qualifications
  • Experience with PAM4 SERDES and DSP based architectures
  • Experience with PCIE Gen4 protocol level testing and PCI sig compliance

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