Technical Staff Engineer-Design Implementation
Job Description
Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.
Visit our careers page to see what exciting opportunities and company perks await!
Job Description:
Microchip’s MPU group offers microprocessors which rightly balance the performance, power, cost and comes with advanced security capabilities which caters to a multitude of applications. With a broad set of peripherals and interfaces, these MPUs can support a wide range of applications. Point of sales systems, home and industrial automation systems, automotive infotainment etc. are just a few among various supported end uses.
As a Design Implementation Engineer in the MPU32 group, you will work with our multi-sited global Silicon Development Team in design and implementation of complex SoCs. The Implementation Engineer will take part to the development of multi-million, multi-voltage designs. He/She will be expert in Synthesis, Formal Proof, UPF/CPF flows targeting Signoff quality. The candidate will also have a good knowledge and experience of timing constraints, STA and DFT insertion.
This position requires a proactive and highly motivated candidate, with strong technical skills, and a proven record of success in a multi-site and multi-functional team environment.
The position could evolve towards management. Therefore, mentorship and leadership skills are a plus.
Responsibilities
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Perform and optimize Synthesis of hierarchical achieving high QoS of multi-voltage designs,
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Perform Formal Proof, debug, and understand FP results, handle SOC modelling constraints until FP is reached,
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Drive low-power implementation and optimization using UPF/CPF description with Front-End team support,
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Perform CLP flow, analyze and debug CLP checks for valid power definition,
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Perform DFT Insertion (Scan, OCC, BSD) based on DFT team specification,
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Perform and validate functional ECOs,
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Interact with and support Front-End, STA and Back-End teams,
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Collaborate with Methodology team for continuous flow development and improvement,
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Collaborate with cross-functional teams to ensure timely delivery of high-quality designs.
Requirements/Qualifications:
Requirements
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Bachelor’s or master’s degree in electronics engineering or related field,
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15+ years of experience in SoC Design Implementation,
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Deep knowledge and strong experience of Synthesis, Formal Proof Low power flow, UPF/CPF (Synopsys DC, Cadence LEC and CLP)
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Good understanding of timing constraints and STA flow,
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Good understanding of DFT concepts and constraints,
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Previous experience and proficiency in any one of commonly used scripting languages (Perl, Python , TCL)
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Knowledge of revision control mechanisms, Â
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Excellent analytical and problem-solving skills,
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Strong communication and collaboration skills,
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First experience in management is a plus.
Travel Time:
0% - 25%
Date Posted
11/28/2024
Views
0
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