Design and develop innovative HBM memory subsystem architectures for AI/ML solutions collaborating with multi-functional teams and evaluating IP vendors.

Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence inspiring the world to learn communicate and advance faster than ever.
Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity sustainability and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.
You will be responsible for the design & development of next generation HBM DRAM products. You will join a highly multi-functional group of technical experts. They work closely with customers partners and a distributed team from Engineering Process Development Package Engineering and Business Units. Together you will work toward a shared goal of making our future HBM roadmap successful.
The HBM Design Architecture group is looking for an experienced Memory Subsystem Architect to work with internal and external partners to investigate define and develop innovative new memory subsystem architectures building on our Industry leading HBM product solutions. The AI/ML transformation underway demands breakthrough memory and computing solutions. We believe our HBM product roadmap is foundational in enabling these new exciting solutions. The HBM Design Architecture group collaborates closely with Industry partners to investigate and develop products aligned with customer needs and technology trends extending over 3-5 year timeframe.
Responsibilities

• Develop innovative memory subsystem architectures for HBM-based AI/ML solutions including PHY memory controllers NOC microcontrollers MBIST interfaces adapters RAS and support for DDR/LPDDR/HBM memory types.
• Define Memory and RAS architecture requirements and drive end-to-end architectural specification for next-generation memory subsystems.
• Collaborate with internal and external partners to develop novel architectures and detailed IP requirements across all memory subsystem components.
• Lead engagement with IP vendors including evaluation and selection of interface IP and functional IP blocks.
• Analyze benchmarks workloads and simulation results to identify performance and efficiency innovation opportunities in memory subsystems.
• Perform performance and performance/Watt modeling; estimate gate count power and area; and generate architectural and external-facing specifications aligned with hardware/protocol standards.
• Partner with RTL validation and multi-functional teams to ensure successful and timely implementation of subsystem features contributing to technical reviews for HBM and memory products.
• Drive microarchitecture definition participate in performance simulation and benchmarking and debug issues across high-level models RTL simulation and hard/soft IP.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering Computer Engineering or a related field.
• Minimum of 10 years of experience in memory subsystem architecture and design.
• Deep understanding of memory controller design and memory types (DDR LPDDR GDDR HBM).
• Experience with PHY design and understanding of signal integrity issues.
• Proficiency in Network-on-Chip (NoC) architecture and design.
• Familiarity with industry-standard bus protocols such as AXI AMBA AHB DFI HIF etc
• Strong analytical and problem-solving skills
• Excellent written and verbal communication skills

Preferred Qualifications

• A PhD in a relevant field or equivalent experience
• Familiarity with EDA tools for design and verification
• Practical experience with multi-core systems coherent interconnects & Industry IO protocol like PCIe/CXL confidential compute virtualization & security
• Knowledge of serial link protocols (UCIe etc.) is desired

The US base salary range that Micron Technology estimates it could pay for this full-time position is:
$146000.00 - $309000.00 a year
Additional compensation may include benefits bonuses and equity.
Our salary ranges are determined by role level and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range individual pay is determined by work location and additional job-related factors including knowledge skills experience tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only and do not include bonus equity or benefits.
As a world leader in the semiconductor industry Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well provide peace of mind and help you prepare for the future. We offer a choice of medical dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury and paid family leave. Additionally Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available please see the Benefits Guide posted on micron.com/careers/benefits .
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race color religion sex sexual orientation age national origin citizenship status disability protected veteran status gender identity or any other factor protected by applicable federal state or local laws.
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