Principal Silicon System On Chip Architect

Microsoft is a leader in developing world-class devices and silicon. Microsoft's Silicon team develops custom silicon accelerators and System on Chips (SOCs) for Microsoft's server and client devices that enable planet-scale human empowerment.

Come join our dynamic and collaborative Silicon Architecture team. We are looking for a passionate Principal System on Chip (SoC) Silicon Architect to make an impact delivering silicon solutions with their experience in high-performance SOC architecture, informed by their past Central Processing Unit (CPU) and/or Graphics Processing Units (GPU) architecture and design.

You will follow your best practices in building complex state-of-the-art SOCs in leading silicon technology nodes. This position is expected to be highly visible and impactful. The breadth of architectural domains in our silicon architecture team provides the perfect opportunity to utilize your intellectual curiosity to grow and increase your impact. You will be expected to be on-site at least 50% of the time to help mentor and lead silicon engineers, as well as collaborate with internal customers and partners. We support and encourage flexible, hybrid work.

Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

We are committed to a diverse and inclusive workplace and strongly encourage applicants from all backgrounds and walks of life. Difference makes us better.

Qualifications:

Required/Minimum Qualifications

• 9+ years of related technical engineering experience
  o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.

• 8+ years of experience in the field of computer architecture in three or more of the following areas: CPU, GPU, Network on Chip (NoC), Machine Learning (ML), text/lossless compression, memory subsystems, and Peripheral component interconnect express
  (PCIe).
• 3+ years Register-Transfer Level (RTL) d esign and micro-architecture experience.

Background Check Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Understanding or experience in security architecture.
• Understanding or experience in packaging technologies.
• Experience working with IP vendors.
• Ability to work with multiple teams with record of collaboration and leadership.
• At least one project as architect carried all the way from incubation through silicon bring up and validation.

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $133,600 - $256,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

Responsibilities:

You will be on the leading edge of computing, building lasting relationships with various cross-functional groups to deliver high-performance and innovative silicon System on Chip (SoC), using your extensive experience to develop hardware architectures and features. You are expected to work with limited direction, pay attention to detail and be able to provide crisp status of progress, issues, and risks on the program to the management team.

Responsibilities include:

• Leading the definition of highly integrated SoC with multiple IPs for competitive Power, Performance, Area (PPA) and Total Cost of Ownership (TCO) optimization, supporting variety of functional use cases as required by the platform.
• Working with IP architects and IP vendors to define the SoC architecture.
• Author sections of architecture specification of the SoC.
• Work with customer hardware and software teams to ensure architecture meets customer needs.
• Work with design, verification, and back-end teams to ensure design meets architecture specification.
• Develop architecture models in C/C++ to measure performance and guide the implementation.
• Develop die area and yield/cost analysis for the SoC.