Senior Silicon Power Engineer

Come join an evolving Microsoft Silicon Engineering team with a growth mindset. We are looking for a n Senior Silicon Power engineer who is passionate about all aspects of power estimation, modelling, and measurement to help Microsoft create power optimal Intellectual Property ( IP) and System on Chip (SoC) solutions.

We're committed to a diverse and inclusive workplace and strongly encourage applicants from all background s and walks of life . Difference makes us better.

Qualifications:

Required/Minimum Qualifications:

• 7+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 5+ years of experience with Register Transfer Level (RTL) and gate-level power analysis/optimization, User Plane Function (UPF), and power-intent verification.
• 5+ years of experience with PrimePower.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred/Additional Qualifications:

• Experience with pre-netlist power estimation tools
• Adept at combining multiple specifications and simulated values to create a full chip power budget and track takedown
• Experience in physically-aware synthesis and static timing analysis
• Experience in post-silicon static/dynamic power measurements and correlation
• Experience in voltage binning or chip Vmin methodologies
• Field-programmable gate array (FPGA) development environment tools experience using Vivado/Quartus tools is a plus
• Good u nderstanding of all power components and their scaling/ variation across silicon process, voltage, temperature ( PVT)
• Good understanding of board -level power distribution and thermal control methodology
• Team player with good communication skills , a growth mindset , and ability to facilitate collabor ation across Microsoft internal groups and external vendors.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

Responsibilities:

• You will be the primary resource for pre-silicon power modelling and estimation as well as post silicon measurement and correlation .
• You will drive power efficient architecture and aid in optimizing Register Transfer Level (RTL) and physical implementation .
• You will work on power estimation tools and methodology .
• You will be providing crisp status of progress, issues, and risks on the program to the management team .
• You will be working independently with limited direction.