Jobs at Cadence
15,385 open positions
Principal Software Engineer
Company: Cadence
Location: Cambridge, United Kingdom
Posted Jan 22, 2025
Cadence is seeking a highly motivated software engineer to join their R&D team in Cambridge, UK. The role involves designing, developing, and supporting the Genus software product, which synthesizes microchip circuits. The company values innovation, leadership, and a passionate work ethic. The Genus Clock Gating Team's algorithms optimize circuit design for clock speed, size, and power efficiency. The team is globally connected, fostering a collaborative culture.
Principal Product Engineer
Company: Cadence
Location: Noida, India
Posted Jan 22, 2025
Cadence, a leader in electronic design, is seeking a Principal Product Engineer with 7-12 years of experience. The role involves working on cutting-edge technology, influencing product development, and managing tool deployment. Cadence offers a collaborative environment, diverse team, and opportunities for growth. The company values employee well-being and provides multiple avenues for learning and development.
IT Associate Desktop Specialist (f/m/d)
Company: Cadence
Location: Munich, Germany
Posted Jan 22, 2025
Software R&D Intern, Summer
Company: Cadence
Location: Austin, TX
Posted Jan 22, 2025
Cadence is seeking a PhD or 2nd year MS intern with a focus on VLSI CAD algorithm development. The ideal candidate should have a master's degree, be pursuing a PhD, and have expertise in physical synthesis problems such as placement, routing, clock tree synthesis, buffering, gate sizing, or logic optimization. The candidate must be a strong coder, capable of prototyping and testing algorithms quickly. An established publication record is preferred.
Lead C++ Software Engineer
Company: Cadence
Location: Toronto, Canada
Posted Jan 22, 2025
Cadence is seeking a skilled C++ software engineer to join their Protium Software Development Team. The role involves developing and enhancing the Protium FPGA-Based Prototyping product, used by leading tech companies for pre-Silicon software validation. Responsibilities include enhancing Static Timing Analysis (STA) in the Protium Compiler, optimizing memory and runtime, and developing the EDA automation flow. The ideal candidate should have a degree in Computer Science, Electrical/Computer Engineering, and at least 4 years of related experience. They should be proficient in C/C++, Verilog or SystemVerilog, and have experience in multi-threaded/concurrent programming. Knowledge of ML/AI algorithms is a plus.
Software Engineer II
Company: Cadence
Location: San Jose, CA
Posted Jan 22, 2025
Cadence is seeking an R&D engineer for a multi-threaded and distributed physical synthesis core engine in the Innovus Implementation System. The role involves designing, developing, and troubleshooting software programs in physical synthesis, collaborating with a global R&D team, and working closely with product engineers/technical sales to provide engineering solutions. The ideal candidate should have C/C++ software development experience in Linux, strong understanding of data structures and algorithms, excellent communication skills, and a MS (Ph.D. track a plus) in Electrical Engineering or Computer Science. Prior experience in physical synthesis algorithms, timing analysis, and multithreading is a plus. The annual salary range is $98,000 to $182,000, with additional incentives and benefits.
Digital Implementation Lead Application Engineer
Company: Cadence
Location: San Jose, CA
Posted Jan 22, 2025
Cadence is seeking talented hardware designers and application engineers to join their North America Field Applications Team. The Lead Application Engineer role involves providing technical support for Digital Implementation and Signoff tools, working closely with customers on advanced nodes, and solving challenges in meeting power, performance, and area (PPA) in various vertical markets. The position offers growth opportunities, including learning about different customer segment requirements and the latest advancements in Machine Learning and 3DIC. Requirements include a Bachelor's degree with at least 6 years of design/EDA experience or a Master's degree with at least 4 years of experience, strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis, and experience with ASIC digital implementation flows and EDA tools. The annual salary range for California is $100,100 to $185,900, with additional incentive compensation and benefits.